ASIC: Gate Arrays, Embedded Arrays and Standard Cells
TOPICS
Latest Activities
- Development of 150 nm and 130 nm process products commenced
- Technology that achieves ultralow power consumption
- Offering system solutions by utilizing ISB packages
ASIC
Gate Arrays
LC24xxx,LC22xxx Series
- Short development period
- Development cost can be minimized
- Gates are arranged in advance in an array structure on the chip.
- These gates are then connected using metal interconnects to form logic circuits.
- Support for 0.6µm, 0.35µm product series
Embedded Arrays
LC274xx, LC273xx, LC272xx, LC27xxx Series
- Short development period possible
- High degree of design flexibility
- Effective from a mass production cost standpoint
- First, the number of gates and the type and number of megacells are determined.
- The megacells are arranged on the master.
- Other areas have the same structure as gate arrays, and the masters are stocked prior to the interconnect process.
- After logic verification, the IC is completed in the same way as gate arrays, i.e. by the formation of metal interconnects.
- SANYO provides an extensive set of megacells.
- Support for 0.6µm, 0.35µm, 0.25µm, 0.18µm product series
Standard Cells
LC98700, LC98600, LC98500, LC98300 Series
- High degree of design flexibility
- Effective from a mass production cost standpoint
- ICs are completed by arranging and connecting specially designed function cells and previously provided megacells.
- Megacells with even higher levels of functionality can also be included.
- SANYO provides an extensive set of megacells.
- Support for 0.6µm, 0.35µm, 0.25µm, 0.18µm product series
